Modern computer systems are often designed to operate with multiple processors communicating with a shared memory. The processors and the memory communicate through a system bus. Also, input and output modules are usually connected to the system bus.
The design of a processor module, hereinafter referred to as a CPU module, often includes a cache memory. The cache memory provides fast local memory data to the processor chip. Typically, the CPU module incorporates a module-level processor bus. The components of the CPU module often include the CPU processor chip, a system interface which connects directly to the system bus, and the cache memory; and these components communicate using the processor bus.
The protocol in the module level processor bus is determined, in many cases, by the design of the processor chip. An often utilized protocol for the processor chip is that the processor chip serves as a bus master, and other components on the processor bus serve as slaves. A frequently used protocol is that the processor chip responds to a single "bus request" line and provides a grant signal on a single "bus grant" line. Receipt of the bus grant signal by another component connected to the processor bus permits the other component to gain control of the bus and perform transactions. When only a processor chip and a system interface chip compete for control of the bus, this simple control system is adequate, as the system interface chip may control the cache.
In previous designs, using the less complex cache write-through protocol, there is no requirement that the cache control chip obtain control of the processor bus. The cache control chip need only respond to signals on the processor bus, and control is managed by the system interface, as disclosed by Sullivan, et al, "The VAX 6000 Model 400 Scalar Processor Module", in Digital Technical Journal Vol. 2, No. 2, Spring 1990, Pages 27-35; and Durdan, et al, "An Overview of the VAX 6000 Model 400 Chip Set", Digital Technical Journal, Vol. 2, No. 2, Pages 36-51, Spring 1990. The processor chip and the system interface can function with a simple master-slave protocol with the processor chip responding to a single "bus request" line and granting access to the bus on a single "bus grant" line.
However, in a more complex control system having a cache write-back protocol, the simple master slave control of the processor bus may prove inadequate because a more complex control protocol is required. For example, the more complex control protocol of a cache write-back system may require a cache control chip to be added to the CPU module, and then there are at least three chips competing for access to the processor bus: the processor chip; the system interface; and the cache control chip. For three separate chips competing for access to the processor bus, the single master slave protocol is inadequate. And the single master slave protocol is particularly inadequate in the situation where the processor does not have any simple provision for acquiring the information necessary to decide whether the cache control chip or the system interface should gain access to the processor bus; and further where the processor has no simple way of granting control of the processor bus to a selected one of, the cache control chip or the system interface.